Category: Workshop

  • FPGA Night 16 July (7-10PM)

    We will be designing VHDL code to send data to an SN74HC595N shift register. If time permits we will create a design that reads the output of the shift register at higher speeds (> 1MHz) until the register begins to send invalid data. Because of the cost of FPGA dev boards, we will not have…

  • FPGA Night (2 July 7-10PM)

    We will be creating a generic entity to drive a seven segment display and then use push buttons to control the seven segment (count up and count down). Required Items: 1. Laptop with Xilinx ISE installed. Please ensure you already have the ISE installed!! We will not have time to wait for the install process…

  • FPGA Night (25 June 7-10PM)

    We will be using push buttons to interface with the FPGA as well as learning how to debounce the inputs. If time permits, we will also cover First In First Out (FIFO) buffers. Required Items: 1. Laptop with Xilinx ISE installed. Please ensure you already have the ISE installed!! We will not have time to…

  • FPGA Night (18 June, 7-10PM)

    We will be continuing the LCD interface project. The goal for the night will be to build the parent process for driving the finite state machine and sending commands to the LCD. Required Items: 1. Laptop with Xilinx ISE installed. Please ensure you already have the ISE installed!! We will not have time to wait…

  • Arduino Night (14 June, 7-10PM)

    This will be a repeat of the last class on LCD interfacing. Several people were unable to make it last time, so we will be covering it one more time. Required Items: Laptop Arduino USB cable for your Arduino Breadboard Jumpers for breadboard Provided Items: LCD If you need any items in the required items…

  • FPGA Night (11 June, 7-10PM)

    We will be starting the LCD interface project. The goal for the night will be to get the finite state machine running properly. Required Items: 1. Laptop with Xilinx ISE installed. Please ensure you already have the ISE installed!! We will not have time to wait for the install process to complete (it usually takes…

  • FPGA Night (4 June 7-10PM)

    We will be covering interfacing with 7 segment displays. This is the precursor to the next class which will cover interfacing with 2×20 character LCD screens. Agenda: 1. Determine pinout of 7 segment display 2. Create a map of the pins 3. Flash all segments at once 4. Create a ROM lookup table to count…

  • UnalloCTF Wrap-up

    UnalloCTF, it happened, it was awesome. We had 13 teams participate, 6 of which were remote. There were about 30 flags on 11 targets for a total of 4800 possible points. Points of entry were available for most Pen Testing Skillsets: Web Exploitation Service Exploitation SQL Injection Direct Database Login Telnet We had a separate…

  • FPGA Night (28 May, 7-10PM)

    We will be covering building custom blocks and then using them in VHDL modules. If time permits, we will also cover using outside input in the form of push buttons. Agenda: 1. Design a module that slows down an input clock 2. Design a module that uses the above module to blink an LED at…

  • Java Certification Study Group (1 June 7:30-10PM)

    Session number 2. We will be covering chapters 1 and 2 out of  http://www.amazon.com/SCJP-Certified-Programmer-Java-310-065/dp/0071591060.